1. Field of the Invention
The present invention relates to a through silicon via (TSV) and a method of forming the same, and more particularly, to a TSV having a buffer layer and a method of forming the same.
2. Description of the Prior Art
In the modern society, the micro-processor systems comprising integrated circuits (IC) are ubiquitous devices, being utilized in diverse fields such as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increase of original applications for electronical products, the IC devices are becoming smaller, more delicate and more diversified.
As well known in the art, an IC device is produced from dies that are fabricated by conventional semiconductor manufacturing processes. The process for manufacturing a die starts with a wafer: first, different regions are marked on the wafer; secondly, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are used to form the needed circuit trace(s); then, each region of the wafer is separated to form a die, and packaged to form a chip; finally, the chip is attached onto a board, a printed circuit board (PCB), for example, and the chip is electrically coupled to the pins on the PCB. Thus, each function on the chip can be performed.
In order to evaluate the functions and the efficiency of the chip and increase the capacitance density to accommodate more IC components in a limited space, many semiconductor package technologies built up each die and/or chip by stacking, for example, Flip-Chip technology, Multi-chip Package (MCP) technology, Package on Package (PoP) technology and Package in Package (PiP) technology. Besides these technologies, a “Through Silicon Via (TSV)” technique has been developed in recent years. TSV can improve the interconnections between chips in the package so as to increase the package efficiency. However, since TSV is usually made of copper, which coefficient of thermal expansion (CTE) and the tensile modulus are very different from those of the silicon substrate, a lot of problems arise.